In general, crystalline materials may be classified as single-crystalline (or single crystal), polycrystalline (or poly-crystal) or as amorphous, or as combinations thereof, based on their crystal structure. A single crystalline material is one that has a single crystal unit structure, while a polycrystalline material has a structure comprising a plurality of crystal units. An amorphous material does not include a defined crystal structure, as atoms in amorphous materials may be irregularly bonded to each other. A polycrystalline material typically has many grain boundaries due to the plurality of crystal structure units. The movement of carriers such as electrons and holes may be restricted by these grain boundaries.
In order to reduce and/or minimize such reductions in carrier mobility, single crystalline silicon layers are often used, for example, as the active region of thin film transistors (TFT) that have a stacked structure. A single crystalline silicon layer is one that includes a high density of relatively large single crystal grains. It will be appreciated by those of skill in the art that polycrystalline layers may also have a plurality a single crystal units contained therein, but the size of the grains and the density of large grains is substantially smaller. Generally, a layer is considered to comprise a single crystalline semiconductor layer as opposed to a polycrystalline (or other) layer when the layer contains a high density of single crystal grains that exhibit long-range translational symmetry.
To form a single crystal silicon layer, an amorphous silicon layer may be formed on an insulation layer, and a heat treatment is performed on the amorphous silicon layer to form the single crystalline silicon layer. Methods of forming single crystalline silicon layers are disclosed, for example, in Japanese Patent Publication No. 2001-308008, Japanese Patent Publication No. 2002-359159 and U.S. Pat. No. 5,972,105.
In the method disclosed in Japanese Patent Publication No. 2001-308008, an amorphous silicon layer is formed on a silicon substrate. The amorphous silicon layer is then heat treated in a furnace that is maintained, for example, at a temperature of about 500° C. to about 700° C. As a result of this heat treatment, a silicide layer is formed on a surface of the silicon substrate to thereby obtain the single crystalline silicon layer. The above Japanese Publication Patent discloses methods of forming single crystalline silicon layers that both do and do not use a silicon seed.
When a single crystalline silicon layer is formed without a silicon seed according to the methods disclosed in the above-referenced Japanese patent publication, it may be difficult to enlarge the grain in the single crystalline silicon layer because the nucleation sites may be randomly distributed in the amorphous silicon layer. While it may be easier to enlarge the grain size of the single crystals when the single crystalline silicon layer is formed using a silicon seed, processing failures may be generated on a boundary surface of the silicon substrate.
Japanese Patent Publication No. 2002-359159 discloses a method of forming a single crystal silicon layer in which an amorphous silicon layer is formed into a seed by a first heat treatment that is applied using a laser. The amorphous silicon layer is then formed into a single crystalline silicon layer by a second heat treatment that is also applied using a laser. This method may involve the use of a photoresist pattern during the first heat treatment that forms the seed, and the method may use the laser twice in forming the single crystalline silicon layer.